This invention relates to a bit circuit for use in programmable logic arrays formed on integrated-circuit chips and, in particular, to what is commonly known as a "zero-power" bit circuit formed using complementary-metal-oxide-semiconductor (CMOS) processes.
Known previous attempts at constructing zero-power bit circuits in integrated form have utilized either cross-coupled inverters with stable states skewed by capacitors connected to power sources or have utilized CMOS technology related to electrically-erasable-programmable-read-only-memory (EEPROM) devices. Bit circuits using cross-coupled inverters depend upon well-controlled power-up sequences for proper initialization of the circuit at the time the power source is connected and, if the bit setting is disturbed by unwanted transients occurring during operation, resetting of the bit will not occur until the next such power-up sequence is applied to the circuit. Bit circuits formed using EEPROM technology are generally limited to use in circuit designs that have EEPROM capability.
Accordingly, there is a need for a zero-power bit circuit that is compatible with existing CMOS erasable programmable read-only-memory (EPROM) processing technology and that requires no special power-up sequence of signals.